1. Field of the Invention
The invention relates to a semiconductor device, in particular, an ESD protection circuit having a high ESD protection characteristic.
2. Description of the Related Art
Conventionally, for addressing ESD, various types of semiconductor devices including ESD protection circuits have been proposed. Typically, as shown in FIG. 4A, an internal circuit 56 is protected by connecting a PN junction diode 53 between an input output terminal 50 and a power supply line 51, connecting a PN junction diode 54 between the input output terminal 50 and a ground line 52, and connecting a PN junction diode 55 between the power supply line 51 and the ground line 52. It is noted that the ESD means the discharge of static electricity and is an abbreviation of Electro-Static Discharge.
For example, even when a large surge voltage is applied to the power supply line 51, the high breakdown voltage PN junction diode 55 is used to discharge an ESD current to the ground line 52 by the avalanche breakdown of the PN junction diode 55. Since an unnecessary current does not flow until the avalanche breakdown occurs, the tolerance to power supply noise is also high.
FIG. 4B shows a relation between a surge voltage and an ESD current by TLP current I and TLP voltage V. It is noted that the TLP is an abbreviation of a Transmission Line Pulse. The TLP will be described below. In a case of a high breakdown voltage diode, the resistance to an ESD current after avalanche breakdown is high, and the ESD current increases, forming a gentle gradient as shown by a line a in FIG. 4B. Therefore, voltages at both the ends of this resistor are large, and it is difficult to protect the internal circuit completely.
In detail, when a large surge voltage is applied to the power supply line 51, the PN junction diode 55 breaks down in an avalanche state, and an ESD current flows from the power supply line 51 toward the ground line 52. At this time, the diode 55 that breaks down in an avalanche state becomes a large resistor for the ESD current, and generates a high voltage between the power supply line 51 and the ground line 52.
A high voltage generated between the power supply line 51 and the ground line 52 is directly applied to the internal circuit. This results in avalanche breakdown or the like of devices forming the internal circuit, causing difficulty in safety design against ESD. Furthermore, since this high voltage is applied between the power supply line 51 and the ground line 52, a leakage current flows by a parasitic transistor or the like.
This is solved by increasing the area of the diode so as to decrease the resistance. As a result, a current easily flows as shown by a line b in FIG. 4B, and an ESD current is quickly discharged to the ground line 52.
However, as the miniaturization of elements is enhanced for a demand for higher speed and smaller size or the like, the electrostatic breakdown tolerance of a semiconductor device is decreased and thus a more proper ESD protection element is essential. Japanese Patent Application publication No. 2006-128293 discloses a BiCMOS type integrated circuit including a MOS type transistor as a high breakdown voltage element and an NPN bipolar transistor as a low breakdown voltage element, in which the low breakdown voltage NPN transistor is used as an ESD protection element.
Furthermore, Japanese Patent Application publication No. Hei 05-90481 discloses using an NPN bipolar transistor provided between a power supply line and a ground line as an ESD protection element, in which the base and the emitter are connected by a resistor, instead of using a PN junction diode. Japanese Patent Application publication No. Hei 06-177328 discloses decreasing a trigger voltage for the snapback characteristic of a MOS type transistor used as an ESD protection element so as to enhance the ESD protection characteristic.
The snapback characteristic means a response of a device to an ESD pulse or the like, and includes a response of a parasitic element. For example, when a high breakdown voltage PN junction diode is used as a protection element between a power supply line and a ground line, a voltage to start the ESD protection is called a trigger voltage. When a necessary ESD current flows, if a voltage occurring between both the terminals of the PN junction diode is lower than a voltage that breaks the internal circuit, the internal circuit is protected from ESD. These relevant techniques are disclosed in Japanese Patent Application publication No. 2006-128293, No. Hei 05-90481 and No. Hei 06-177328.
As described above, with the progression of miniaturization, various ESD protection circuits that protect the internal circuits from ESD have been developed. In Japanese Patent Application publication No. 2006-128293, No. Hei 05-90481 and No. Hei 06-177328 described above, the types and structures of protection elements forming an ESD protection circuit are improved so as to enhance the ESD protection characteristic. However, it is also important to enhance the ESD protection characteristic by forming an ESD protection circuit with such protection elements and devising a circuit structure as well as by developing protection elements in themselves.